In testing semiconductor IC devices by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test generated in response to the test signals. The output signals are strobed, i.e., sampled by strobe signals with predetermined timings or delay times to be compared with expected data to determine whether the IC device functions correctly.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based test system. In a cycle based test system, the semiconductor device (DUT) is tested by providing a cycled pin pattern vectors at a programmed data rate (tester cycle) to a formatter with timing edges to produce desired wave forms such as test signals and strobe signals.
Generally, the various timings of the tester cycles, test signals and strobe signals are generated based on a reference clock. The reference clock (also referred to as "system clock" or "master clock") is produced by a high stable oscillator, such as a crystal oscillator provided in the IC tester. When the required timing resolution of an IC tester is equal to or an integer multiple of the highest clock rate (shortest clock cycle) of a reference clock oscillator, timing signals can be generated by simply dividing the reference clock signal by a counter or a divider and synchronizing the divided output with the reference clock.
However, modern IC testers are usually required to have timing resolution higher than the highest clock rate, i.e., the shortest time period, of a reference clock. For example, there is a case in which a reference clock used in the IC tester 10 ns (nanosecond), but the IC tester needs to have timing resolution of 0.1 ns. Furthermore, the IC testers today dynamically change such various timings in a cycle by cycle basis based on a test program.
To generate such timing signals with the timing resolution higher than the reference clock rate, it is known in the prior art that such timings are described by timing data in a test program. The timing data is a combination of an integer multiple of the reference clock time interval and a fraction of the reference clock time interval. Such timing data is stored in a timing memory and read out at each cycle of the test cycle. Thus, in each test cycle, test signals and strobe signals are generated with reference to the test cycle, such as a start point of each cycle, based on the timing data.
There is another type of test system called an event based test system wherein the desired test signals and strobe signals are produced by data from an event memory directly on a per pin basis. In an event based test system, events, which are any changes in the logic state, such as rising and fallings of test signals and strobe signals, are defined with respect to time length from predetermined reference time points. Typically, such reference time points are timings of previous events such as shown in the example of FIG. 1. For producing high resolution timings, the time length between the events is defined by a combination of an integer multiple of a reference clock time interval and a fraction of the reference clock time interval.
In the example of FIG. 1, the first event (logical change) occurs at a point a which is a time T0 after a start time. For convenience of explanation, the first event is designated by T0. The second event (hereinafter event T1) occurs at a point b which is a time T1 after the point a. The third event (hereinafter event T2) occurs at a point c which is a time T2 after the point b. Likewise, events T0-T10 are shown in the example of FIG. 1.
In an event based test system, since the timing data in a timing memory (event memory) does not need to include each and every test cycle data, description of the timing data is dramatically simplified. In the event based test system, usually, the timing data for each event stored in an event memory is expressed by a time difference between the current event and the last event. Usually, such a time difference between the adjacent events is small, a size of the data in the memory can also be small, resulting in the reduction of the memory capacity.
Moreover, in the computer aided design (CAD) system widely used today for designing semiconductor devices such as an LSI and VLSI, a logic simulator in the CAD system utilizes event based test signals for evaluating the semiconductor device. Therefore, an event based test system shows a better linking ability between the design data produced by the CAD system in the design stage and the test signals to be generated using the design data.
To generate event based test signals for testing complicated and high performance semiconductor devices, a large volume of event data must be stored in an event memory. Accordingly, there is a need to establish a way of compressing the event data to store the data in the event memory and decompressing the event data from the event memory to generate the event based test signals.